[PATCH 0/3] Add support for enabling PLLs and add GE3D clock/reset entries

[Prabhakar <prabhakar.csengg@xxxxxxxxx>]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi All,

This patch series introduces support for enabling PLL clocks in the
RZ/V2H(P) CPG family driver and adds clock and reset entries for the
GE3D module.

Lad Prabhakar (3):
  clk: renesas: rzv2h-cpg: Move PLL access macros to source file
  clk: renesas: rzv2h-cpg: Add support for enabling PLLs
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D

 drivers/clk/renesas/r9a09g057-cpg.c | 14 +++++++
 drivers/clk/renesas/rzv2h-cpg.c     | 61 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     |  4 +-
 3 files changed, 76 insertions(+), 3 deletions(-)

-- 
2.43.0