On Fri, 7 Feb 2025 at 12:37, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
> - The TINT register base offset is 0x800 instead of zero.
> - The number of GPIO interrupts for TINT selection is 141 instead of 86.
> - The pin index and TINT selection index are not in the 1:1 map.
> - The number of TSSR registers is 16 instead of 8.
> - Each TSSR register can program 2 TINTs instead of 4 TINTs.
>
> Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
> adding LUT for mapping between pin index and TINT selection index.
>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v3->v4:
> * Updated commit description fixing typos
> * Updated rzg3e_hw_params with .field_width and dropped .tien,
> .tssel_mask,.tssel_shift, .tssr_k as it can be derived from former.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
