On Fri, 7 Feb 2025 at 12:37, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs > for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and > ICU_TSSR_TSSEL_MASK. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> For the logical change: Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds