Hello Nikita-san,
> From: Nikita Yushchenko, Sent: Monday, December 9, 2024 5:00 PM
>
> MPIC.PIS must be set per phy interface type.
> MPIC.LSC must be set per speed.
>
> Do that strictly per datasheet, instead of hardcoding MPIC.PIS to GMII.
>
> Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Switch"")
> Signed-off-by: Nikita Yushchenko <nikita.yoush@xxxxxxxxxxxxxxxxxx>
Thank you for the patch! I could not apply this patch on net.git / main branch
and the branch + your patches [1] though, this patch looks good. So,
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
[1]
https://patchwork.kernel.org/project/netdevbpf/list/?series=915669
Best regards,
Yoshihiro Shimoda
> ---
> drivers/net/ethernet/renesas/rswitch.c | 27 ++++++++++++++++++++------
> drivers/net/ethernet/renesas/rswitch.h | 14 ++++++-------
> 2 files changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
> index 7f17b9656cc3..6ca5f72193eb 100644
> --- a/drivers/net/ethernet/renesas/rswitch.c
> +++ b/drivers/net/ethernet/renesas/rswitch.c
> @@ -1124,25 +1124,40 @@ static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)
>
> static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
> {
> - u32 val;
> + u32 pis, lsc;
>
> rswitch_etha_write_mac_address(etha, mac);
>
> + switch (etha->phy_interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + pis = MPIC_PIS_GMII;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_5GBASER:
> + pis = MPIC_PIS_XGMII;
> + break;
> + default:
> + pis = FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC));
> + break;
> + }
> +
> switch (etha->speed) {
> case 100:
> - val = MPIC_LSC_100M;
> + lsc = MPIC_LSC_100M;
> break;
> case 1000:
> - val = MPIC_LSC_1G;
> + lsc = MPIC_LSC_1G;
> break;
> case 2500:
> - val = MPIC_LSC_2_5G;
> + lsc = MPIC_LSC_2_5G;
> break;
> default:
> - return;
> + lsc = FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC));
> + break;
> }
>
> - iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);
> + rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC,
> + FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc));
> }
>
> static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
> diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
> index 741b089c8523..abcf2aac49cd 100644
> --- a/drivers/net/ethernet/renesas/rswitch.h
> +++ b/drivers/net/ethernet/renesas/rswitch.h
> @@ -725,13 +725,13 @@ enum rswitch_etha_mode {
>
> #define EAVCC_VEM_SC_TAG (0x3 << 16)
>
> -#define MPIC_PIS_MII 0x00
> -#define MPIC_PIS_GMII 0x02
> -#define MPIC_PIS_XGMII 0x04
> -#define MPIC_LSC_SHIFT 3
> -#define MPIC_LSC_100M (1 << MPIC_LSC_SHIFT)
> -#define MPIC_LSC_1G (2 << MPIC_LSC_SHIFT)
> -#define MPIC_LSC_2_5G (3 << MPIC_LSC_SHIFT)
> +#define MPIC_PIS GENMASK(2, 0)
> +#define MPIC_PIS_GMII 2
> +#define MPIC_PIS_XGMII 4
> +#define MPIC_LSC GENMASK(5, 3)
> +#define MPIC_LSC_100M 1
> +#define MPIC_LSC_1G 2
> +#define MPIC_LSC_2_5G 3
>
> #define MPSM_PSME BIT(0)
> #define MPSM_MFF BIT(2)
> --
> 2.39.5
