Hi Geert, Thank you for the review. On Fri, Jul 26, 2024 at 4:09 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Mon, Jul 15, 2024 at 12:37 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > We are using devres APIs for divider, mux and pll5 clocks so for > > consistency use the devres APIs for module, fixed factor and PLL clocks. > > > > While at it switched to clk_hw_register() instead of clk_register() > > as this has been marked as deprecated interface. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > --- > > v1->v2 > > - Propagate error code from rzg2l_cpg_pll_clk_register() if > > devm_clk_hw_register() fails > > - Used devm_clk_hw_register_fixed_factor() for fixed factor clock > > - Set error pointer in rzg2l_cpg_register_mod_clk() if > > devm_clk_hw_register() failed > > Thanks for the update! > > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -1116,6 +1121,8 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, > > clk = of_clk_get_by_name(priv->dev->of_node, core->name); > > break; > > case CLK_TYPE_FF: > > + struct clk_hw *clk_hw; > > I will move this up while applying, to match the style of the rest of > the file. > Good point, thanks for taking care of it. Cheers, Prabhakar
