From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Hi, This patch series aims to refactor and simplify the clock registration code in the Renesas RZ/G2L CPG (Clock Pulse Generator) driver. The changes enhance consistency, simplify function signatures, and remove redundant parameters, thereby improving maintainability and reducing potential for errors. v1->v2 - Propagate error code from rzg2l_cpg_pll_clk_register() if devm_clk_hw_register() fails - Used devm_clk_hw_register_fixed_factor() for fixed factor clock - Set error pointer in rzg2l_cpg_register_mod_clk() if devm_clk_hw_register() failed - Squashed patches (2,3,4)/4 into single patch - Dropped masking of parent clock with 0xffff - Dropped creating local variable clks v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240628131021.177866-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ Cheers, Prabhakar Lad Prabhakar (2): clk: renesas: rzg2l-cpg: Use devres API to register clocks clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register functions drivers/clk/renesas/rzg2l-cpg.c | 72 +++++++++++++++++---------------- 1 file changed, 38 insertions(+), 34 deletions(-) -- 2.34.1
