The custom clock driver that models PLL clocks on R-Car Gen4 supports
variable clocks, while PLL1 uses a similar control register layout, but
is read-only.
Extend the existing support to fixed clocks and PLL1, and introduce a
new clock type and helper macro to describe a fixed PLL.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
---
v2:
- Add Reviewed-by.
---
drivers/clk/renesas/rcar-gen4-cpg.c | 32 ++++++++++++++++++++---------
drivers/clk/renesas/rcar-gen4-cpg.h | 4 ++++
2 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 7f95231ccee8bd11..1f3dddbd294a572b 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -179,6 +179,10 @@ static int cpg_pll_8_25_clk_set_rate(struct clk_hw *hw, unsigned long rate,
val & pll_clk->pllecr_pllst_mask, 0, 1000);
}
+static const struct clk_ops cpg_pll_f8_25_clk_ops = {
+ .recalc_rate = cpg_pll_8_25_clk_recalc_rate,
+};
+
static const struct clk_ops cpg_pll_v8_25_clk_ops = {
.recalc_rate = cpg_pll_8_25_clk_recalc_rate,
.determine_rate = cpg_pll_8_25_clk_determine_rate,
@@ -188,13 +192,15 @@ static const struct clk_ops cpg_pll_v8_25_clk_ops = {
static struct clk * __init cpg_pll_clk_register(const char *name,
const char *parent_name,
void __iomem *base,
- unsigned int index)
+ unsigned int index,
+ const struct clk_ops *ops)
{
static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = {
- [2 - 2] = { CPG_PLL2CR0, CPG_PLL2CR1 },
- [3 - 2] = { CPG_PLL3CR0, CPG_PLL3CR1 },
- [4 - 2] = { CPG_PLL4CR0, CPG_PLL4CR1 },
- [6 - 2] = { CPG_PLL6CR0, CPG_PLL6CR1 },
+ [1 - 1] = { CPG_PLL1CR0, CPG_PLL1CR1 },
+ [2 - 1] = { CPG_PLL2CR0, CPG_PLL2CR1 },
+ [3 - 1] = { CPG_PLL3CR0, CPG_PLL3CR1 },
+ [4 - 1] = { CPG_PLL4CR0, CPG_PLL4CR1 },
+ [6 - 1] = { CPG_PLL6CR0, CPG_PLL6CR1 },
};
struct clk_init_data init = {};
struct cpg_pll_clk *pll_clk;
@@ -205,13 +211,13 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
return ERR_PTR(-ENOMEM);
init.name = name;
- init.ops = &cpg_pll_v8_25_clk_ops;
+ init.ops = ops;
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
- pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 2].cr0;
- pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 2].cr1;
+ pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 1].cr0;
+ pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 1].cr1;
pll_clk->pllecr_reg = base + CPG_PLLECR;
pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
@@ -413,7 +419,7 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
* modes.
*/
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
- base, 2);
+ base, 2, &cpg_pll_v8_25_clk_ops);
case CLK_TYPE_GEN4_PLL2:
mult = cpg_pll_config->pll2_mult;
@@ -445,9 +451,15 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
break;
+ case CLK_TYPE_GEN4_PLL_F8_25:
+ return cpg_pll_clk_register(core->name, __clk_get_name(parent),
+ base, core->offset,
+ &cpg_pll_f8_25_clk_ops);
+
case CLK_TYPE_GEN4_PLL_V8_25:
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
- base, core->offset);
+ base, core->offset,
+ &cpg_pll_v8_25_clk_ops);
case CLK_TYPE_GEN4_Z:
return cpg_z_clk_register(core->name, __clk_get_name(parent),
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index d02e61911bfc6903..69436309f19dfff2 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -19,6 +19,7 @@ enum rcar_gen4_clk_types {
CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL5,
CLK_TYPE_GEN4_PLL6,
+ CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */
CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */
CLK_TYPE_GEN4_SDSRC,
CLK_TYPE_GEN4_SDH,
@@ -48,6 +49,9 @@ enum rcar_gen4_clk_types {
#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
+#define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx)
+
#define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx)
--
2.34.1
