Hi Geert, Thank you for the review. On Fri, Jul 12, 2024 at 3:08 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Fri, Jun 28, 2024 at 3:11 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and > > `base` parameters in various clock registration functions. These values > > are now accessed directly from the `priv` structure. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -400,10 +400,10 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct rzg2l_cpg_pri > > > > static struct clk * __init > > rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, > > - struct clk **clks, > > - void __iomem *base, > > struct rzg2l_cpg_priv *priv) > > { > > + void __iomem *base = priv->base; > > + struct clk **clks = priv->clks; > > If "clks" is used only once in a function, then please use priv->clks[...] > directly instead of adding another local variable. > This applies to other functions in this patch. > Ok, I'll update it. > BTW, why did you decide to have separate patch [2/4], [3/4], and [4/4]? > They all follow the same pattern. > I split them up for easier review. But I'll squash them now. Cheers, Prabhakar