Hi Geert, Thank you for the review. On Fri, Jul 12, 2024 at 2:55 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Fri, Jun 28, 2024 at 3:11 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > We are using devres APIs for divider, mux and pll5 clocks so for > > consistency use the devres APIs for module and PLL clocks. > > > > While at it switched to clk_hw_register() instead of clk_register() > > as this has been marked as deprecated interface. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, > > struct clk_init_data init; > > const char *parent_name; > > struct pll_clk *pll_clk; > > + int ret; > > > > parent = clks[core->parent & 0xffff]; > > if (IS_ERR(parent)) > > @@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, > > pll_clk->priv = priv; > > pll_clk->type = core->type; > > > > - return clk_register(NULL, &pll_clk->hw); > > + ret = devm_clk_hw_register(dev, &pll_clk->hw); > > + if (ret) > > + return NULL; > > rzg2l_cpg_pll_clk_register() can return an ERR_PTR, so please > propagate the error code. > Ok, I'll propagate the error. Cheers, Prabhakar