Hi Prabhakar,
On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add family-specific clock driver for RZ/V2H(P) SoCs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3
> - Dropped num_hw_resets from struct rzv2h_cpg_priv
> - Dropped range_check for module clocks
> - Made mon_index to s8 instead of u8 in struct rzv2h_mod_clk
> - Added support for critical module clocks with DEF_MOD_CRITICAL
> - Added check for mon_index in rzv2h_mod_clock_endisable and
> rzv2h_mod_clock_is_enabled()
Thanks for the update!
> --- /dev/null
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> +static struct clk * __init
> +rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
> + struct rzv2h_cpg_priv *priv,
> + const struct clk_ops *ops)
> +{
> + void __iomem *base = priv->base;
> + struct clk **clks = priv->clks;
> + struct device *dev = priv->dev;
> + struct clk_init_data init;
> + const struct clk *parent;
> + const char *parent_name;
> + struct pll_clk *pll_clk;
> +
> + parent = clks[core->parent & 0xffff];
No need to mask with 0xffff, as nothing is ever stored in the high bits.
> +static void __init
> +rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> + struct rzv2h_cpg_priv *priv)
> +{
> + struct mod_clock *clock = NULL;
> + struct device *dev = priv->dev;
> + struct clk_init_data init;
> + unsigned int id = mod->id;
This is the sole user of mod->id, which can be calculated easily from
mod->on_index and mod->on_bit.
> --- /dev/null
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> +/**
> + * struct rzv2h_mod_clk - Module Clocks definitions
> + *
> + * @name: handle between common and hardware-specific interfaces
> + * @parent: id of parent clock
> + * @id: clock index in array containing all Core and Module Clocks
> + * @critical: flag to indicate the clock is critical
> + * @on_index: control register index
> + * @on_bit: ON bit
> + * @mon_index: monitor register index
> + * @mon_bit: monitor bit
> + */
> +struct rzv2h_mod_clk {
> + const char *name;
> + unsigned int parent;
> + unsigned int id;
No need to store the id, as it can be calculated when needed.
> + bool critical;
> + u8 on_index;
> + u8 on_bit;
> + s8 mon_index;
> + u8 mon_bit;
That leaves us with 1 64-bit pointer, 1 32-bit integer, and 5 bytes.
Using bitfields for the latter is complicated due to the mix of signed
and unsigned values.
However, parent can be reduced to u16, shaving off one 64-bit word
from each entry.
> +};
> +/**
> + * struct rzv2h_reset - Reset definitions
> + *
> + * @reset_index: reset register index
> + * @reset_bit: reset bit
> + * @mon_index: monitor register index
> + * @mon_bit: monitor bit
> + */
> +struct rzv2h_reset {
> + u8 reset_index;
> + u8 reset_bit;
> + u8 mon_index;
> + u8 mon_bit;
> +};
> +
> +#define RST_ID(x, y) ((((x) * 16)) + (y))
> +
> +#define DEF_RST_BASE(_id, _resindex, _resbit, _monindex, _monbit) \
> + [_id] = { \
Indexing by _id means the reset array will be very sparse. E.g. the
innocent-looking r9a09g057_resets[] with only a single entry takes
600 bytes.
If you do need the full array for indexing, please allocate and
populate it at runtime.
As a bonus, you would no longer need rzv2h_cpg_info.info, and
r9a09g057_resets[] and r9a09g057_cpg_info[] can become __initconst.
> + .reset_index = (_resindex), \
> + .reset_bit = (_resbit), \
> + .mon_index = (_monindex), \
> + .mon_bit = (_monbit), \
> + }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
