Hi Prabhakar,
On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Document the device tree bindings for the Renesas RZ/V2H(P) SoC
> Clock Pulse Generator (CPG).
>
> CPG block handles the below operations:
> - Generation and control of clock signals for the IP modules
> - Generation and control of resets
> - Control over booting
> - Low power consumption and power supply domains
>
> Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
> core clocks are a subset of the ones which are listed as part of section
> 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3
> - Dropped '|' for CPG description
> - Dropped description for '#power-domain-cells' property
> - Added 3 clock inputs for CPG
> - Dropped label in example node
> - Used 4 spaces for example node
> - Renamed r9a09g057-cpg.h -> renesas,r9a09g057-cpg.h
> - Merged adding renesas,r9a09g057-cpg.h in DT binding patch
> - Updated commit message
Thanks for the update!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> + '#clock-cells':
> + description: |
> + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> + and a core clock reference, as defined in
> + <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> + a module number. The module number is calculated as the CLKON register
> + offset index multiplied by 16, plus the actual bit in the register
> + used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
> + calculation is (1 * 16 + 3) = 19.
Using hexadecimal for the final number may be more readable,
also in the DTS?
(1 * 16 + 3) = 0x13?
> + const: 2
> +
> + '#power-domain-cells':
> + const: 0
> +
> + '#reset-cells':
> + description:
> + The single reset specifier cell must be the reset number. The reset number
> + is calculated as the reset register offset index multiplied by 16, plus the
> + actual bit in the register used to reset the specific IP block. For example,
> + for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 48.
(3 * 16 + 0) = 0x30?
> --- /dev/null
> +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
__DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
[...]
> +#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */
__DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
