Hi Prabhakar,
On Tue, Jun 4, 2024 at 5:49 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Document the device tree bindings of the Renesas RZ/V2H(P) SoC
> > Clock Pulse Generator (CPG).
> >
> > CPG block handles the below operations:
> > - Handles the generation and control of clock signals for the IP modules
> > - The generation and control of resets
> > - Control over booting
> > - Low power consumption and the power supply domains
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> > +
> > + '#clock-cells':
> > + description: |
> > + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> > + and a core clock reference, as defined in
> > + <dt-bindings/clock/r9a09g057-cpg.h>,
> > + - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> > + a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> > + const: 2
>
> I understand this will be changed to 1, the clock number?
We typically come up with our own definitions in header files if there
are no suitable module numbers listed in the hardware documentation.
For RZ/V2H, you could use a combination (e.g. concatenation) of the
column (register) and row (bit) numbers from Tables 4.4-14-19
("Specifications of the CPG_CLKON_m Registers") and Tables 4.4-22-25
("Specifications of the CPG_RST_m Registers") as the clock resp. reset
number, like is done on R-Car Gen2+ SoCs (see MOD_CLK_PACK() for
conversion from sparse to packed module numbers).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
