Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Thomas Gleixner <tglx@xxxxxxxxxxxxx>]

On Tue, Apr 30 2024 at 15:14, Prabhakar wrote:
> +
> +static void rzfive_irqc_irq_disable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, false);
> +	irq_chip_disable_parent(d);
> +}
> +
> +static void rzfive_irqc_irq_enable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, true);
> +	irq_chip_enable_parent(d);
> +}

This looks wrong. Enable/disable should be symmetric vs. ordering, no?

Thanks,

        tglx