From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Hi All, The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found on the RZ/G2L family of SoCs. IAX45 performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral interrupts output by each module. And it notifies the interrupt to the PLIC. - Select 32 TINT from 82 GPIOINT. - Integration of bus error interrupts from system bus. - Integration of ECC error interrupts from On-chip RAM. - Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt and integrated ECC error interrupt) - Setting of interrupt detection method. (NMI, IRQ and TINT) - All interrupts are masked by INTMASK. - Mask function for NMI, IRQ and TINT This patch series adds support for IAX45 in the IRQC driver and enables this on RZ/Five SoC. v3->v4 - Renamed rzg2l_irqc_init_helper -> rzg2l_irqc_common_init - Moved the locks into callers for (un)mask and (en/dis)able functions - Collected RB tag from Geert for patch#2 v2->v3 - DTS/I patches dropped from the series as they have been merged into renesas-soc tree - Just using a const from compat string instead of having it in a items - Added RZ/Five specific irqchip v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240403203503.634465-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC irqchip/renesas-rzg2l: Add support for RZ/Five SoC .../renesas,rzg2l-irqc.yaml | 17 +- drivers/irqchip/irq-renesas-rzg2l.c | 148 +++++++++++++++++- 2 files changed, 155 insertions(+), 10 deletions(-) -- 2.34.1
