Hi Geert,
Thanks for your patch.
On 2024-03-19 17:29:05 +0100, Geert Uytterhoeven wrote:
> Add device nodes for the Timer Units (TMU) on the R-Mobile APE6 SoC,
> and the clocks serving them.
>
> Note that TMU channels 1 and 2 are not added, as their interrupts are
> not wired to the interrupt controller for the AP-System Core (INTC-SYS),
> only to the interrupt controller for the AP-Realtime Core (INTC-RT).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/renesas/r8a73a4.dtsi | 37 +++++++++++++++++++++++
> include/dt-bindings/clock/r8a73a4-clock.h | 4 +++
> 2 files changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi
> index ac654ff45d0e9a9c..9a2ae282a46ba4b1 100644
> --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi
> +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi
> @@ -60,6 +60,32 @@ timer {
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + tmu0: timer@e61e0000 {
> + compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
> + reg = <0 0xe61e0000 0 0x30>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tuni0", "tuni1", "tuni2";
> + clocks = <&mstp1_clks R8A73A4_CLK_TMU0>;
> + clock-names = "fck";
> + power-domains = <&pd_c5>;
> + status = "disabled";
> + };
> +
> + tmu3: timer@fff80000 {
> + compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
> + reg = <0 0xfff80000 0 0x30>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tuni0", "tuni1", "tuni2";
> + clocks = <&mstp1_clks R8A73A4_CLK_TMU3>;
> + clock-names = "fck";
> + power-domains = <&pd_a3r>;
> + status = "disabled";
> + };
> +
> dbsc1: memory-controller@e6790000 {
> compatible = "renesas,dbsc-r8a73a4";
> reg = <0 0xe6790000 0 0x10000>;
> @@ -654,6 +680,17 @@ extal1_div2_clk: extal1_div2 {
> };
>
> /* Gate clocks */
> + mstp1_clks: mstp1_clks@e6150134 {
> + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
> + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
> + clocks = <&cp_clk>, <&mp_clk>;
> + #clock-cells = <1>;
> + clock-indices = <
> + R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3
> + >;
> + clock-output-names =
> + "tmu0", "tmu3";
> + };
> mstp2_clks: mstp2_clks@e6150138 {
> compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
> reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
> diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h
> index 1ec4827b80916054..655440a3e7c6868a 100644
> --- a/include/dt-bindings/clock/r8a73a4-clock.h
> +++ b/include/dt-bindings/clock/r8a73a4-clock.h
> @@ -24,6 +24,10 @@
> #define R8A73A4_CLK_ZS 14
> #define R8A73A4_CLK_HP 15
>
> +/* MSTP1 */
> +#define R8A73A4_CLK_TMU0 25
> +#define R8A73A4_CLK_TMU3 21
> +
> /* MSTP2 */
> #define R8A73A4_CLK_DMAC 18
> #define R8A73A4_CLK_SCIFB3 17
> --
> 2.34.1
>
--
Kind Regards,
Niklas Söderlund
