On 27/02/2024 01:40, Niklas Söderlund wrote:
> To make it possible to merge the R-Car and RZ/G2L code paths move the
> maximum usable size of a single Rx descriptor data slice in to the
> hardware information instead of using two different defines in the two
> different code paths.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> drivers/net/ethernet/renesas/ravb.h | 5 +----
> drivers/net/ethernet/renesas/ravb_main.c | 12 ++++++++----
> 2 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index 7fa60fccb6ea..b12b379baf5a 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1015,10 +1015,6 @@ enum CSR2_BIT {
> #define NUM_RX_QUEUE 2
> #define NUM_TX_QUEUE 2
>
> -#define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16))
> -
> -#define GBETH_RX_DESC_DATA_SIZE 4080
> -
> struct ravb_tstamp_skb {
> struct list_head list;
> struct sk_buff *skb;
> @@ -1058,6 +1054,7 @@ struct ravb_hw_info {
> int stats_len;
> u32 tccr_mask;
> u32 rx_max_frame_size;
> + u32 rx_max_desc_use;
> unsigned aligned_tx: 1;
>
> /* hardware features */
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index b309ca23f5b6..dee51a78cf36 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -349,7 +349,7 @@ static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
> for (i = 0; i < priv->num_rx_ring[q]; i++) {
> /* RX descriptor */
> rx_desc = &priv->rx_ring[q].desc[i];
> - rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
> + rx_desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
> dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
> priv->info->rx_max_frame_size,
> DMA_FROM_DEVICE);
> @@ -379,7 +379,7 @@ static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
> for (i = 0; i < priv->num_rx_ring[q]; i++) {
> /* RX descriptor */
> rx_desc = &priv->rx_ring[q].ex_desc[i];
> - rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
> + rx_desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
> dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
> priv->info->rx_max_frame_size,
> DMA_FROM_DEVICE);
> @@ -919,7 +919,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
> for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
> entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
> desc = &priv->rx_ring[q].desc[entry];
> - desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
> + desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
>
> if (!priv->rx_skb[q][entry]) {
> skb = ravb_alloc_skb(ndev, info);
> @@ -1034,7 +1034,7 @@ static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
> for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
> entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
> desc = &priv->rx_ring[q].ex_desc[entry];
> - desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
> + desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use);
>
> if (!priv->rx_skb[q][entry]) {
> skb = ravb_alloc_skb(ndev, info);
> @@ -2692,6 +2692,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = {
> .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
> .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
> .rx_max_frame_size = SZ_2K,
> + .rx_max_desc_use = 2048 - ETH_FCS_LEN + sizeof(__sum16),
I'd prefer that we use SZ_2K here instead of 2048 for consistency with the line above.
> .internal_delay = 1,
> .tx_counters = 1,
> .multi_irqs = 1,
> @@ -2717,6 +2718,7 @@ static const struct ravb_hw_info ravb_gen2_hw_info = {
> .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
> .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
> .rx_max_frame_size = SZ_2K,
> + .rx_max_desc_use = 2048 - ETH_FCS_LEN + sizeof(__sum16),
As above.
> .aligned_tx = 1,
> .gptp = 1,
> .nc_queues = 1,
> @@ -2739,6 +2741,7 @@ static const struct ravb_hw_info ravb_rzv2m_hw_info = {
> .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
> .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
> .rx_max_frame_size = SZ_2K,
> + .rx_max_desc_use = 2048 - ETH_FCS_LEN + sizeof(__sum16),
As above.
> .multi_irqs = 1,
> .err_mgmt_irqs = 1,
> .gptp = 1,
> @@ -2763,6 +2766,7 @@ static const struct ravb_hw_info gbeth_hw_info = {
> .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
> .tccr_mask = TCCR_TSRQ0,
> .rx_max_frame_size = SZ_8K,
> + .rx_max_desc_use = 4080,
> .aligned_tx = 1,
> .tx_counters = 1,
> .carrier_counters = 1,
--
Paul Barker
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