From: Duy Nguyen <duy.nguyen.rh@xxxxxxxxxxx> Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@xxxxxxxxxxx> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> --- Changes compared to the BSP: - Rename L3_CA76_0 label to L3_CA76, - Rename cache-controller-0 node to cache-controller. --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index eb555cbf51a41001..f47695158d991288 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -23,6 +23,14 @@ a76_0: cpu@0 { reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; -- 2.34.1