Re: [PATCH] clk: renesas: r9a07g043: Add clock and reset entries for CRU

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

On Tue, Jan 23, 2024 at 12:44 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add CRU clock and reset entries to CPG driver.
>
> CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
> sequence for the CRU block hence add these clocks to
> r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for
> RZ/G2UL SoCs.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.9.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds