On Thu, Nov 16, 2023 at 07:00:00PM +0000, Biju Das wrote: > Hello Uwe, > > The clock rate for RZ/G2L family SoCs is 100 MHz. > > With this, maximum possible period in nsec = 2^32 * 10 nsecs * 1024 (prescale) = 43,980,465,111,040 nsec which is well below than > 2^64. > > So I am planning to reject the PWM Period > 43,980,465,111,040 nsecs in apply on next version. > > Please correct me, if It is wrong. It's wrong. A request for a period > 43,980,465,111,040 ns should configure 43,980,465,111,040 then. (Rationale: If your HW could do 43,980,465,111,040 and 50,000,000,000,000 (and nothing in between) and you request 44,000,000,000,000 you get 43,980,465,111,040, right? That your hardware cannot do 50,000,000,000,000 is totally irrelevant for this request and the resulting configuration. So go with 43,980,465,111,040 even if you cannot do 50,000,000,000,000.) Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |
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