Hi Wolfram,
On Fri, Sep 29, 2023 at 8:14 AM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> From: Dirk Behme <dirk.behme@xxxxxxxxxxxx>
>
> The clock dividers might be used with clock stop bit enabled or not.
> Current tables only support recommended values from the datasheet. This
> might result in warnings like below because no valid clock divider is
> found. Resulting in a 0 divider.
>
> There are Renesas ARM Trusted Firmware version out there which e.g.
> configure 0x201 (shifted logical right by 2: 0x80) and with this match
> the added { STPnHCK | 0, 1 }:
>
> https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108
>
> ------------[ cut here ]------------
> sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70
> Modules linked in:
> CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1
> Hardware name: Custom board based on r8a7796 (DT)
> pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : divider_recalc_rate+0x48/0x70
> ...
> ------------[ cut here ]------------
>
> Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling")
> Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxxxxx>
> [wsa: extended the table to 5 entries, added comments, reword commit message a little]
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
Thanks for your patch!
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v6.7.
> --- a/drivers/clk/renesas/rcar-cpg-lib.c
> +++ b/drivers/clk/renesas/rcar-cpg-lib.c
> @@ -70,8 +70,20 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
> #define STPnHCK BIT(9 - SDnSRCFC_SHIFT)
>
> static const struct clk_div_table cpg_sdh_div_table[] = {
> - { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 },
> - { STPnHCK | 4, 16 }, { 0, 0 },
> + /*
> + * These values are recommended by the datasheet. Because they come
> + * first, Linux will only use these.
> + */
> + { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 }, { STPnHCK | 4, 16 },
Would you mind if I would wrap this to 80 columns (like the original)
while applying?
> + /*
> + * These values are not recommended because STPnHCK is wrong. But they
> + * have been seen because of broken firmware. So, we support reading
> + * them but Linux will sanitize them when initializing through
> + * recalc_rate.
> + */
> + { STPnHCK | 0, 1 }, { STPnHCK | 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 },
> + /* Sentinel */
> + { 0, 0 }
> };
>
> struct clk * __init cpg_sdh_clk_register(const char *name,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
