Hi Geert,
> Subject: Re: [PATCH v4] arm64: dts: renesas: rz-smarc-common: Use versa3
> clk for audio mclk
>
> Hi Biju,
>
> On Fri, Aug 25, 2023 at 11:05 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of
> 44.1kHz).
> > Replace this fixed clk with the programmable versa3 clk that can
> > provide the clocking to support both 44.1kHz (with a clock of
> > 11.2896MHz) and 48kHz (with a clock of 12.2880MHz), based on audio
> > sampling rate for playback and record.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v3->v4:
> > * Dropped clock-output-names from dtsi files.
> > * Updated example with dropping clock-output-names.
>
> Thanks for the update!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > @@ -105,6 +105,26 @@ &i2c3 {
> >
> > status = "okay";
> >
> > + versa3: versa3@68 {
>
> clock-generator@ (everywhere)
OK.
>
> > + compatible = "renesas,5p35023";
> > + reg = <0x68>;
> > + #clock-cells = <1>;
> > + clocks = <&x1>;
> > +
> > + renesas,settings = [
> > + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
> > + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
> > + 80 b0 45 c4 95
> > + ];
> > +
> > + assigned-clocks = <&versa3 0>, <&versa3 1>,
> > + <&versa3 2>, <&versa3 3>,
> > + <&versa3 4>, <&versa3 5>;
> > + assigned-clock-rates = <24000000>, <11289600>,
> > + <11289600>, <12000000>,
> > + <25000000>, <12288000>;
> > + };
>
> Please move this node down, to preserve sort order (by unit-address).
>
> Same comments arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
>
> Unless we're gonna need a new iteration for some other reason (the
> corresponding fixes for the clock index order are not yet in linux-next), I
> can fix the above while applying...
Thank you
Cheers,
Biju
