As per kernel documentation, use raw_spinlock_t only in real critical core code, low-level interrupt handling, and places where disabling preemption or interrupts is required. Here the lock is for concurrent register access from different drivers, hence spin_lock() is sufficient. Reported-by: Pavel Machek <pavel@xxxxxxx> Closes: https://patchwork.kernel.org/project/linux-renesas-soc/patch/20230717120333.165219-1-biju.das.jz@xxxxxxxxxxxxxx/ Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> --- This patch depend upon [1] [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20230717120333.165219-1-biju.das.jz@xxxxxxxxxxxxxx/ --- drivers/mfd/rz-mtu3.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index e5cace963c7c..2400bf5830b9 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -21,7 +21,7 @@ struct rz_mtu3_priv { void __iomem *mmio; struct reset_control *rstc; - raw_spinlock_t lock; + spinlock_t lock; }; /******* MTU3 registers (original offset is +0x1200) *******/ @@ -175,11 +175,11 @@ void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset, struct rz_mtu3_priv *priv = mtu->priv_data; unsigned long tmdr, flags; - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tmdr = rz_mtu3_shared_reg_read(ch, offset); __assign_bit(pos, &tmdr, !!val); rz_mtu3_shared_reg_write(ch, offset, tmdr); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); } EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit); @@ -255,13 +255,13 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start) bitpos = rz_mtu3_get_tstr_bit_pos(ch); /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tstr = rz_mtu3_shared_reg_read(ch, offset); __assign_bit(bitpos, &tstr, start); rz_mtu3_shared_reg_write(ch, offset, tstr); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); } bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) @@ -276,9 +276,9 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) bitpos = rz_mtu3_get_tstr_bit_pos(ch); /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tstr = rz_mtu3_shared_reg_read(ch, offset); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); return tstr & BIT(bitpos); } @@ -348,7 +348,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) return PTR_ERR(ddata->clk); reset_control_deassert(priv->rstc); - raw_spin_lock_init(&priv->lock); + spin_lock_init(&priv->lock); platform_set_drvdata(pdev, ddata); for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) { -- 2.25.1
