Hi Serge,
> From: Serge Semin, Sent: Wednesday, July 12, 2023 5:48 AM
>
> On Wed, Jul 05, 2023 at 08:41:55PM +0900, Yoshihiro Shimoda wrote:
> > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > field there is another one which needs to be updated. It's
> > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > the very least the maximum link-width capability CSR won't expose
> > the actual maximum capability.
> >
> > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.60a, March 2015, p.1032
> > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.70a, March 2016, p.1065
> > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.90a, March 2016, p.1057
> > ...
> > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > Version 5.40a, March 2019, p.1396
> > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 5.40a, March 2019, p.1266
> >
>
> > The commit description is suggested by Serge Semin.
>
> This is implied by the Suggested-by tag. I'd drop it.
I got it.
> Anyway. The change looks good to me. Thanks!
> Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
Thank you very much for your review!
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Suggested-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 7b720bad7656..44150d34720a 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> >
> > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > {
> > - u32 lwsc, plc;
> > + u32 lnkcap, lwsc, plc;
> > + u8 cap;
> >
> > if (!num_lanes)
> > return;
> > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > }
> > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > +
> > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > }
> >
> > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > --
> > 2.25.1
> >
