Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH] arm64: dts: renesas: r9a07g0{4,5}4: Add support for
> enabling MTU3
>
> Hi Biju,
>
> On Wed, Jul 5, 2023 at 3:06 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > > Subject: Re: [PATCH] arm64: dts: renesas: r9a07g0{4,5}4: Add support
> > > for enabling MTU3 On Mon, Jul 3, 2023 at 3:29 PM Biju Das
> > > <biju.das.jz@xxxxxxxxxxxxxx>
> > > wrote:
> > > > Add support for MTU3 macro to enable MTU3 node on RZ/{G2,V2}L
> > > > SMARC
> > > EVK.
> > > >
> > > > The MTU3a PWM pins are muxed with spi1 pins and counter external
> > > > input phase clock pins are muxed with scif2 pins. Disable these
> > > > IPs when
> > > > MTU3 macro is enabled.
> > > >
> > > > Apart from this, the counter Z phase clock signal is muxed with
> > > > the
> > > > SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase
> > > > signal is enabled.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
>
> > > > +&mtu3_pins {
> > > > + mtu3-zphase-clk {
> > > > + pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A
> */
> > > > + };
> > > > +};
> > >
> > > With the #defines moved up, mtu3-zphase-clk can be moved to
> > > mtu3_pins in rzg2l-smarc-pinfunction.dtsi.
> >
> > Z-phase support is added only for cascade counter(MTU1 + MTU2)
> >
> > I thought by making this as optional, SDHI + standalone MTU1 or MTU2
> > can still work. That is the reason it is moved here.
> >
> > If we move "mtu3-zphase-clk" to mtu3_pins in
> > rzg2l-smarc-pinfunction.dtsi Either
> >
> > we need to make MTU3 mutually exclusive with SDHI
> >
> > Or
> >
> > Guard "mtu3-zphase-clk" with "MTU3_COUNTER_Z_PHASE_SIGNAL" macro in
> > rzg2l-smarc-pinfunction.dtsi.
> >
> > Which one I need to select??
>
> I'd go for the #ifdef, as you had above.
OK.
>
> > > > +
> > > > +&sdhi1 {
> > > > + status = "disabled";
> > > > +};
> > > > +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
> > >
> > > BTW, how does the driver know it can use the counter Z phase clock
> > > signal? I understand this can be either an input or output signal?
> >
> > It is an input signal and is supported only for the cascade(MTU1 +
> MTU2) operation. When we supply z-phase signal(By inserting SD card or
> applying a voltage to cd pin on the sd connector), counter value gets
> cleared.
>
> The documentation for MTIOC1A says:
>
> MTU1 TGRA input capture input/output compare output/PWM output pin
>
> So the output functions are not yet supported by the driver?
For Z-Phase, Counter clear function is TGRALW/TGRBLW input capture, when we
set MTU1 & MTU2(LWA = 1)
We are supporting output function for PWM, but it is not tested with MTIOC1A
pin. So far the output functions(PWM) are tested with MTIOC{3A,3C} as it is available on PMOD0.
Cheers,
Biju
