Hi Biju,
On Thu, May 18, 2023 at 5:23 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> As per RZ/G2L HW(Rev.1.30 May2023) manual, there is no "write enable"
> bits for CPG_SIPLL5_CLK1 register. So fix the CPG_SIPLL5_CLK register
> write by removing "write enable" bits.
>
> Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -603,10 +603,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> }
>
> /* Output clock setting 1 */
> - writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |
> - CPG_SIPLL5_CLK1_REFDIV_WEN | (params.pl5_postdiv1 << 0) |
> - (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
> - priv->base + CPG_SIPLL5_CLK1);
> + writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
> + (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
>
> /* Output clock setting, SSCG modulation value setting 3 */
> writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
Matches the documentation, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
But I guess the actual CPG_SIPLL5_CLK1_*_WEN bit definitions
should be removed, too? I can do that while applying...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
