Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Note that the BSP went to great lengths to describe this clock as a
programmable Z clock, like on most other R-Car Gen3 SoCs, but add a
quirk to the Z clock driver to use a fixed divider when running on
R-Car V3M.
According to R-Car Series, 3rd Generation Hardware User’s Manual Rev.
2.30 and earlier, the SYS-CPU divider on R-Car V3M is a fixed divider.
Furthermore, the Frequency control register C, which is used on other
SoCs to control the SYS-CPU divider, is documented not to exist (but
empirical evidence shows that it does exist, and that the Z2FC field
works as expected).
---
drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index 0f59c84229a8b8ce..7e90e94c4b68821b 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
--
2.34.1
