Hi Uwe,
> Subject: RE: [PATCH v12 6/6] pwm: Add Renesas RZ/G2L MTU3a PWM driver
>
> Hi Uwe,
>
> Thanks for feedback.
>
> > Subject: Re: [PATCH v12 6/6] pwm: Add Renesas RZ/G2L MTU3a PWM driver
> >
> > Hello Biju,
> >
> > On Wed, Feb 15, 2023 at 10:31:20AM +0000, Biju Das wrote:
> > > > On Thu, Feb 02, 2023 at 04:57:32PM +0000, Biju Das wrote:
> > > > > Add support for RZ/G2L MTU3a PWM driver. The IP supports
> > > > > following PWM modes
> > > > >
> > > > > 1) PWM mode{1,2}
> > > > > 2) Reset-synchronized PWM mode
> > > > > 3) Complementary PWM mode{1,2,3}
> > > >
> > > > It's unclear to me what "PWM mode1" and the other modes are. I
> > > > suspect this is some chip specific naming that isn't
> > > > understandable for outsiders? Would be great to explain that a bit
> more.
> > >
> > > I will give some details about PWM modes mentioned in the HW manual
> here.
> > > I will respond to other comments later.
> > >
> > > PWM Mode 1
> > > ------------
> > > n = {0,1,2,3,4,6,7}
> > > MTIOC0A:-MTU0 TGRA input capture input/output compare output/PWM
> > > output pin
> > > TGRA: Timer General Register A
> > > TIOR: Timer I/O control register
> > > In PWM mode 1, PWM waveforms in up to 12 phases can be output
> > >
> > > PWM waveforms are output from the MTIOCnA and MTIOCnC pins by
> > > pairing TGRA with TGRB and TGRC with TGRD. The levels specified by
> > > the TIOR.IOA[3:0] and IOC[3:0] bits are output from the MTIOCnA and
> > > MTIOCnC pins at compare matches A and C, and the level specified by
> > > the TIOR.IOB[3:0] and IOD[3:0] bits are output at compare matches B
> > > and D (n = 0 to 4, 6, 7). The initial output value is set in TGRA or
> > > TGRC. If the values set in paired TGRs are identical, the output
> > > value
> > does not change even when a compare match occurs.
> > >
> > > PWM Mode 2
> > > ----------
> > > n = {0,1,2}
> > >
> > > PWM waveform output is generated using one TGR as the cycle register
> > > and the others as duty registers. The level specified in TIOR is
> > > output at
> > compare matches.
> > > Upon counter clearing by a cycle register compare match, the initial
> > > value set in TIOR is output from each pin. If the values set in the
> > > cycle and duty registers are identical, the output value does not
> > > change
> > even when a compare match occurs.
> > >
> > > In PWM mode 2, up to eight phases of PWM waveforms can be output
> > > when synchronous clearing is used as synchronous operation in the
> > > channels that cannot be placed in PWM mode 2.
> >
> > Why is PWM Mode 1 about two outputs? These could be abstracted as two
> > individual PWMs, couldn't they?
Yes, 2 outputs can be model as 2 individual PWM's.
In this mode you could implement a
> > phase shift, but the period is limited to the overflow time of the timers.
Yes, that is correct. For eg:- case MTU0
It has TGRA and TGRB -> MTIOC0A output (PWM0)
TGRC and TGRD -> MTIOC0C output (PWM1)
By using these registers, we can implement phase shift.
Cheers,
Biju
