Hi Uwe,
Thanks for feedback.
> Subject: Re: [PATCH v12 6/6] pwm: Add Renesas RZ/G2L MTU3a PWM driver
>
> Hello Biju,
>
> On Wed, Feb 15, 2023 at 10:31:20AM +0000, Biju Das wrote:
> > > On Thu, Feb 02, 2023 at 04:57:32PM +0000, Biju Das wrote:
> > > > Add support for RZ/G2L MTU3a PWM driver. The IP supports following
> > > > PWM modes
> > > >
> > > > 1) PWM mode{1,2}
> > > > 2) Reset-synchronized PWM mode
> > > > 3) Complementary PWM mode{1,2,3}
> > >
> > > It's unclear to me what "PWM mode1" and the other modes are. I
> > > suspect this is some chip specific naming that isn't understandable
> > > for outsiders? Would be great to explain that a bit more.
> >
> > I will give some details about PWM modes mentioned in the HW manual here.
> > I will respond to other comments later.
> >
> > PWM Mode 1
> > ------------
> > n = {0,1,2,3,4,6,7}
> > MTIOC0A:-MTU0 TGRA input capture input/output compare output/PWM
> > output pin
> > TGRA: Timer General Register A
> > TIOR: Timer I/O control register
> > In PWM mode 1, PWM waveforms in up to 12 phases can be output
> >
> > PWM waveforms are output from the MTIOCnA and MTIOCnC pins by pairing
> > TGRA with TGRB and TGRC with TGRD. The levels specified by the
> > TIOR.IOA[3:0] and IOC[3:0] bits are output from the MTIOCnA and
> > MTIOCnC pins at compare matches A and C, and the level specified by
> > the TIOR.IOB[3:0] and IOD[3:0] bits are output at compare matches B
> > and D (n = 0 to 4, 6, 7). The initial output value is set in TGRA or
> > TGRC. If the values set in paired TGRs are identical, the output value
> does not change even when a compare match occurs.
> >
> > PWM Mode 2
> > ----------
> > n = {0,1,2}
> >
> > PWM waveform output is generated using one TGR as the cycle register
> > and the others as duty registers. The level specified in TIOR is output at
> compare matches.
> > Upon counter clearing by a cycle register compare match, the initial
> > value set in TIOR is output from each pin. If the values set in the
> > cycle and duty registers are identical, the output value does not change
> even when a compare match occurs.
> >
> > In PWM mode 2, up to eight phases of PWM waveforms can be output when
> > synchronous clearing is used as synchronous operation in the channels
> > that cannot be placed in PWM mode 2.
>
> Why is PWM Mode 1 about two outputs? These could be abstracted as two
> individual PWMs, couldn't they? In this mode you could implement a phase
> shift, but the period is limited to the overflow time of the timers.
Please see the PWM Output Registers and Output Pins below [1]
[1] https://paste.pics/7086f969d99b3205b8287e3b328529b9
Here same MTUs have 4 TGR's, in that case it has 2 outputs.
Where as some MTU's have only 2 TGR's, in that case 1 ouput.
Out of 2 TGR's, 1 TGR used for setting cycle and other one for setting duty.
Please see the waveform for PWM mode1 [2]
[2] https://paste.pics/44d75192ca0a8926fdf37796e4fe2915
>
> In Mode 2 the period is more flexible, but no phase shift is possible (apart
> from inversed polarity).
>
> Did I get this right?
Here there is 1 TGR is used for setting cycle and others used for setting duty cycle.
Please see example[2] in pwm mode2 outputting 5-phase PWM waveforms.
[2] https://paste.pics/025f67e874d655d3eebff65ccc123970
>
> > Reset-Synchronized PWM Mode:
> > ---------------------------
> > In the reset-synchronized PWM mode, three phases of positive and
> > negative PWM waveforms (six phases in total) that share a common wave
> > transition point can be output by combining MTU3 and MTU4 and MTU6 and
> MTU7.
> >
> > When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D,
> > MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D, MTIOC6B, MTIOC6D, MTIOC7A,
> > MTIOC7C, MTIOC7B, and MTIOC7D pins function as PWM output pins and
> > timer counters 6 and 12 (MTU3.TCNT and MTU6.TCNT) functions as an
> > up-counter
> >
> >
> > Complementary PWM Mode:
> > ----------------------
> >
> > In complementary PWM mode, dead time can be set for PWM waveforms to be
> output.
> > The dead time is the period during which the upper and lower arm
> > transistors are set to the inactive level in order to prevent short-
> circuiting of the arms.
> > Six positive-phase and six negative-phase PWM waveforms (12 phases in
> > total) with dead time can be output by combining MTU3/ MTU4 and
> > MTU6/MTU7. PWM waveforms without dead time can also be output.
> >
> > In complementary PWM mode, nine registers (compare registers, buffer
> > registers, and temporary registers) are used to control the duty ratio for
> the PWM output.
> >
> > Complementary PWM mode 1 (transfer at crest) Complementary PWM mode 2
> > (transfer at trough) Complementary PWM mode 3 (transfer at crest and
> > trough)
>
> These two modes are more general than the PWM framework supports. There was
> a series some time ago to implement settings with two outputs, but we didn't
> agree on an abstraction and the effort died. So for now these are out of
> scope, right?
I haven't investigated much on complementary PWM, but our Verified Linux Package (VLP)
for RZ/G2L supports it.
I have a plan to add support for atleast complementary PWM mode with output pin
protection(using POE3 module) later similar to GPT[3] with POEG [4].
[3] https://lore.kernel.org/linux-renesas-soc/20230113122343.769329-3-biju.das.jz@xxxxxxxxxxxxxx/
[4] https://lore.kernel.org/linux-renesas-soc/20221215213206.56666-1-biju.das.jz@xxxxxxxxxxxxxx/
Cheers,
Biju
