Hi Biju,
On Thu, Feb 9, 2023 at 5:40 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Enable Renesas at25ql128a flash connected to QSPI0. Also disable
> the node from rzfive-smarc-som as it is untested.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> @@ -179,6 +179,18 @@ eth1_pins: eth1 {
> <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
> };
>
> + qspi0_pins: qspi0 {
> + qspi0-data {
> + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
> + power-source = <1800>;
> + };
> +
> + qspi0-ctrl {
> + pins = "QSPI0_SPCLK", "QSPI0_SSL";
> + power-source = <1800>;
> + };
I guess there is no need for the subnodes, as all pins use the
same power-source value?
> + };
> +
> sdhi0_emmc_pins: sd0emmc {
> sd0_emmc_data {
> pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
> @@ -230,6 +242,38 @@ sd0_mux_uhs {
> };
> };
>
> +&sbc {
> + pinctrl-0 = <&qspi0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <50000000>;
> + spi-tx-bus-width = <1>;
Why not <4>? According to the datasheet, AT25QL128A supports
quad read and write.
> + spi-rx-bus-width = <4>;
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
