Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, but
each cache IPMMU has own module id. So, update descriptions of
renesas,ipmmu-main property for R-Car Gen4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
---
The old R-Car S4-8 datasheet had described IPMMU IMSSTR register, but
the latest datasheet undocumented the register. So, update the propeties
description. Note that the second argument is not used on the driver.
So no behavior change.
.../bindings/iommu/renesas,ipmmu-vmsa.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
index 72308a4c14e7..7f63ecb467e6 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -76,14 +76,15 @@ properties:
items:
- items:
- description: phandle to main IPMMU
- - description: the interrupt bit number associated with the particular
- cache IPMMU device. The interrupt bit number needs to match the main
- IPMMU IMSSTR register. Only used by cache IPMMU instances.
+ - description: The interrupt bit number or module id associated with
+ the particular cache IPMMU device. The interrupt bit number needs
+ to match the main IPMMU IMSSTR register. Only used by cache IPMMU
+ instances.
description:
Reference to the main IPMMU phandle plus 1 cell. The cell is
- the interrupt bit number associated with the particular cache IPMMU
- device. The interrupt bit number needs to match the main IPMMU IMSSTR
- register. Only used by cache IPMMU instances.
+ the interrupt bit number or module id associated with the particular
+ cache IPMMU device. The interrupt bit number needs to match the main
+ IPMMU IMSSTR register. Only used by cache IPMMU instances.
required:
- compatible
--
2.25.1
