Hi Biju,
On Fri, Nov 18, 2022 at 2:16 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM).
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2{M, MA} PWM Timer (PWM)
> +
> +maintainers:
> + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> +
> +description: |
> + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the
> + following functions
> + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
> + * The frequency division ratio for internal counter operation is selectable
> + as PWM_CLK divided by 1, 16, 256, or 2048.
> + * The period as well as the duty cycle is adjustable.
> + * The low-level and high-level order of the PWM signals can be inverted.
> + * The duty cycle of the PWM signal is selectable in the range from 0 to 100%.
> + * The minimum resolution is 20.83 ns.
> + * Three interrupt sources: Rising and falling edges of the PWM signal and
> + clearing of the counter
> + * Counter operation and the bus interface are asynchronous and both can
> + operate independently of the magnitude relationship of the respective
> + clock periods.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a09g011-pwm # RZ/V2M
> + - renesas,r9a09g055-pwm # RZ/V2MA
> + - const: renesas,rzv2m-pwm
> +
> + reg:
> + maxItems: 1
> +
> + '#pwm-cells':
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: CPU Peripheral Group F APB clock
"APB clock"
PWM0-7] are part of Peripheral Group E, and the block might be
reused on SoCs not using CPU Peripheral Group clock signals.
> + - description: PWM clock
> +
> + clock-names:
> + items:
> + - const: apb
> + - const: pwm
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a09g055-pwm
> +then:
> + required:
> + - resets
I think you should make the resets property required unconditionally.
DT describes hardware, not software policy.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
