The RZ/V2{M, MA} PWM Timer (PWM) is composed of 16 channels. Linux is only
allowed access to channels 8 to 14 on RZ/V2M, while there is no restriction
for RZ/V2MA.
The RZ/V2{M, MA} PWM Timer (PWM) supports the following functions:
* The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
* The frequency division ratio for internal counter operation is selectable
as PWM_CLK divided by 1, 16, 256, or 2048.
* The period as well as the duty cycle is adjustable.
* The low-level and high-level order of the PWM signals can be inverted.
* The duty cycle of the PWM signal is selectable in the range from 0 to 100%.
* The minimum resolution is 20.83 ns.
* Three interrupt sources: Rising and falling edges of the PWM signal and
clearing of the counter
* Counter operation and the bus interface are asynchronous and both can
operate independently of the magnitude relationship of the respective
clock periods.
Note:
Hardware manual for this IP can be found here
https://www.renesas.com/in/en/document/mah/rzv2m-users-manual-hardware?language=en
Biju Das (5):
clk: renesas: r9a09g011: Add PWM clock entries
dt-bindings: pwm: Add RZ/V2M PWM binding
pwm: Add support for RZ/V2M PWM driver
arm64: dts: renesas: r9a09g011: Add pwm nodes
arm64: dts: renesas: rzv2m evk: Enable pwm
.../bindings/pwm/renesas,rzv2m-pwm.yaml | 98 +++++
.../boot/dts/renesas/r9a09g011-v2mevk2.dts | 70 ++++
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 91 ++++
drivers/clk/renesas/r9a09g011-cpg.c | 9 +
drivers/pwm/Kconfig | 11 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rzv2m.c | 390 ++++++++++++++++++
7 files changed, 670 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
create mode 100644 drivers/pwm/pwm-rzv2m.c
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2.25.1
