On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> As serial communication requires a clock signal, the Serial
clean clock
> Communication Interfaces with FIFO (SCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
>
> Hence change the clock input for the SCIF Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
>
> Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
> Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
> Reported-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-devel for v6.2, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
