Similar to what Geert found out for V4H, adapt the (H)SCIF clock parents and baud rate generators to the parents mentioned in the updated documentation. Slightly tested with SCIF on the Spider board in Kieran's lab. But the HW engineers already confirmed Geert findings. Wolfram Sang (4): clk: renesas: r8a779f0: Fix HSCIF parent clocks clk: renesas: r8a779f0: Fix SCIF parent clocks arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 16 ++++++++-------- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) -- 2.35.1
