RZ/G2L has separate IRQ lines for tx and error interrupt for each
channel whereas R-Car has a combined IRQ line for all the channel
specific tx and error interrupts.
Add multi_channel_irqs to struct rcar_canfd_hw_info to select the
driver to choose between combined and separate irq registration for
channel interrupts. This patch also removes enum rcanfd_chip_id and
chip_id from both struct rcar_canfd_hw_info, as it is unused.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
drivers/net/can/rcar/rcar_canfd.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index d226eb59010d..0b6f14df2a43 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -41,12 +41,6 @@
#define RCANFD_DRV_NAME "rcar_canfd"
-enum rcanfd_chip_id {
- RENESAS_RCAR_GEN3 = 0,
- RENESAS_RZG2L,
- RENESAS_R8A779A0,
-};
-
/* Global register bits */
/* RSCFDnCFDGRMCFG */
@@ -524,11 +518,11 @@ enum rcar_canfd_fcanclk {
struct rcar_canfd_global;
struct rcar_canfd_hw_info {
- enum rcanfd_chip_id chip_id;
u32 max_channels;
/* hardware features */
unsigned multi_global_irqs:1; /* Has multiple global irqs */
unsigned clk_postdiv:1; /* Has CAN clk post divider */
+ unsigned multi_channel_irqs:1; /* Has multiple channel irqs */
};
/* Channel priv data */
@@ -599,19 +593,17 @@ static const struct can_bittiming_const rcar_canfd_bittiming_const = {
};
static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
- .chip_id = RENESAS_RCAR_GEN3,
.max_channels = 2,
.clk_postdiv = 1,
};
static const struct rcar_canfd_hw_info rzg2l_hw_info = {
- .chip_id = RENESAS_RZG2L,
.max_channels = 2,
.multi_global_irqs = 1,
+ .multi_channel_irqs = 1,
};
static const struct rcar_canfd_hw_info r8a779a0_hw_info = {
- .chip_id = RENESAS_R8A779A0,
.max_channels = 8,
.clk_postdiv = 1,
};
@@ -1755,7 +1747,7 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->can.clock.freq = fcan_freq;
dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
- if (info->chip_id == RENESAS_RZG2L) {
+ if (info->multi_channel_irqs) {
char *irq_name;
int err_irq;
int tx_irq;
--
2.25.1
