Hi Krzysztof Kozlowski,
> Subject: Re: [PATCH RFC 2/8] dt-bindings: mfd: Document RZ/G2L MTU3a
> bindings
>
> On 26/09/2022 15:21, Biju Das wrote:
> > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > channels and one 32-bit timer channel. It supports the following
> > functions
> > - Counter
> > - Timer
> > - PWM
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 275
> ++++++++++++++++++
> > 1 file changed, 275 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > new file mode 100644
> > index 000000000000..c1fae8e8d9f9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > @@ -0,0 +1,275 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
>
> Drop "bindings"
>
> Since this is RFC, not a ready patch, the review is fast and not
> thorough. Please send final patch for review (when ready).
>
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > +
> > +description: |
> > + This hardware block pconsisting of eight 16-bit timer channels
> and
> > +one
> > + 32- bit timer channel. It supports the following specifications:
> > + - Pulse input/output: 28 lines max.
> > + - Pulse input 3 lines
> > + - Count clock 11 clocks for each channel (14 clocks for MTU0,
> 12 clocks
> > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2
> combination
> > + (when LWA = 1))
> > + - Operating frequency Up to 100 MHz
> > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > + - Waveform output on compare match
> > + - Input capture function (noise filter setting available)
> > + - Counter-clearing operation
> > + - Simultaneous writing to multiple timer counters (TCNT)
> > + (excluding MTU8).
> > + - Simultaneous clearing on compare match or input capture
> > + (excluding MTU8).
> > + - Simultaneous input and output to registers in
> synchronization with
> > + counter operations (excluding MTU8).
> > + - Up to 12-phase PWM output in combination with synchronous
> operation
> > + (excluding MTU8)
> > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > + - Buffer operation specifiable
> > + - [MTU1, MTU2]
> > + - Phase counting mode can be specified independently
> > + - 32-bit phase counting mode can be specified for
> interlocked operation
> > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > + - Cascade connection operation available
> > + - [MTU3, MTU4, MTU6, and MTU7]
> > + - Through interlocked operation of MTU3/4 and MTU6/7, the
> positive and
> > + negative signals in six phases (12 phases in total) can
> be output in
> > + complementary PWM and reset-synchronized PWM operation.
> > + - In complementary PWM mode, values can be transferred from
> buffer
> > + registers to temporary registers at crests and troughs of
> the timer-
> > + counter values or when the buffer registers (TGRD
> registers in MTU4
> > + and MTU7) are written to.
> > + - Double-buffering selectable in complementary PWM mode.
> > + - [MTU3 and MTU4]
> > + - Through interlocking with MTU0, a mode for driving AC
> synchronous
> > + motors (brushless DC motors) by using complementary PWM
> output and
> > + reset-synchronized PWM output is settable and allows the
> selection
> > + of two types of waveform output (chopping or level).
> > + - [MTU5]
> > + - Capable of operation as a dead-time compensation counter.
> > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > + - 32-bit phase counting mode specifiable by combining MTU1
> and MTU2 and
> > + through interlocked operation with MTU0/MTU5 and MTU8.
> > + - Interrupt-skipping function
> > + - In complementary PWM mode, interrupts on crests and
> troughs of counter
> > + values and triggers to start conversion by the A/D
> converter can be
> > + skipped.
> > + - Interrupt sources: 43 sources.
> > + - Buffer operation:
> > + - Automatic transfer of register data (transfer from the
> buffer
> > + register to the timer register).
> > + - Trigger generation
> > + - A/D converter start triggers can be generated
> > + - A/D converter start request delaying function enables A/D
> converter
> > + to be started with any desired timing and to be
> synchronized with
> > + PWM output.
> > + - Low power consumption function
> > + - The MTU3a can be placed in the module-stop state.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > + - const: renesas,rzg2l-mtu3
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: MTU0.TGRA input capture/compare match
> > + - description: MTU0.TGRB input capture/compare match
> > + - description: MTU0.TGRC input capture/compare match
> > + - description: MTU0.TGRD input capture/compare match
> > + - description: MTU0.TCNT overflow
> > + - description: MTU0.TGRE compare match
> > + - description: MTU0.TGRF compare match
> > + - description: MTU1.TGRA input capture/compare match
> > + - description: MTU1.TGRB input capture/compare match
> > + - description: MTU1.TCNT overflow
> > + - description: MTU1.TCNT underflow
> > + - description: MTU2.TGRA input capture/compare match
> > + - description: MTU2.TGRB input capture/compare match
> > + - description: MTU2.TCNT overflow
> > + - description: MTU2.TCNT underflow
> > + - description: MTU3.TGRA input capture/compare match
> > + - description: MTU3.TGRB input capture/compare match
> > + - description: MTU3.TGRC input capture/compare match
> > + - description: MTU3.TGRD input capture/compare match
> > + - description: MTU3.TCNT overflow
> > + - description: MTU4.TGRA input capture/compare match
> > + - description: MTU4.TGRB input capture/compare match
> > + - description: MTU4.TGRC input capture/compare match
> > + - description: MTU4.TGRD input capture/compare match
> > + - description: MTU4.TCNT overflow/underflow
> > + - description: MTU5.TGRU input capture/compare match
> > + - description: MTU5.TGRV input capture/compare match
> > + - description: MTU5.TGRW input capture/compare match
> > + - description: MTU6.TGRA input capture/compare match
> > + - description: MTU6.TGRB input capture/compare match
> > + - description: MTU6.TGRC input capture/compare match
> > + - description: MTU6.TGRD input capture/compare match
> > + - description: MTU6.TCNT overflow
> > + - description: MTU7.TGRA input capture/compare match
> > + - description: MTU7.TGRB input capture/compare match
> > + - description: MTU7.TGRC input capture/compare match
> > + - description: MTU7.TGRD input capture/compare match
> > + - description: MTU7.TCNT overflow/underflow
> > + - description: MTU8.TGRA input capture/compare match
> > + - description: MTU8.TGRB input capture/compare match
> > + - description: MTU8.TGRC input capture/compare match
> > + - description: MTU8.TGRD input capture/compare match
> > + - description: MTU8.TCNT overflow
> > + - description: MTU8.TCNT underflow
> > +
> > + interrupt-names:
> > + items:
> > + - const: tgia0
> > + - const: tgib0
> > + - const: tgic0
> > + - const: tgid0
> > + - const: tgiv0
> > + - const: tgie0
> > + - const: tgif0
> > + - const: tgia1
> > + - const: tgib1
> > + - const: tgiv1
> > + - const: tgiu1
> > + - const: tgia2
> > + - const: tgib2
> > + - const: tgiv2
> > + - const: tgiu2
> > + - const: tgia3
> > + - const: tgib3
> > + - const: tgic3
> > + - const: tgid3
> > + - const: tgiv3
> > + - const: tgia4
> > + - const: tgib4
> > + - const: tgic4
> > + - const: tgid4
> > + - const: tgiv4
> > + - const: tgiu5
> > + - const: tgiv5
> > + - const: tgiw5
> > + - const: tgia6
> > + - const: tgib6
> > + - const: tgic6
> > + - const: tgid6
> > + - const: tgiv6
> > + - const: tgia7
> > + - const: tgib7
> > + - const: tgic7
> > + - const: tgid7
> > + - const: tgiv7
> > + - const: tgia8
> > + - const: tgib8
> > + - const: tgic8
> > + - const: tgid8
> > + - const: tgiv8
> > + - const: tgiu8
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
>
> Why do you need these two? There are no children here.
On the next 2 patches children added. Good point will move this to next patch.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - power-domains
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + mtu3: timer@10001200 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "renesas,r9a07g044-mtu3", "renesas,rzg2l-mtu3";
> > + reg = <0x10001200 0xb00>;
>
> Order of properties: compatible, reg, then the rest.
OK, will fix this in next version.
Cheers,
Biju
