Hi Biju, On Wed, Sep 21, 2022 at 7:22 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > > Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder > > nodes > > On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > wrote: > > > Just ignore my mail, As I realised IRQ property in each node will be > > a problem. > > > > > Yes the IRQ numbers are different (offset of 32) along with the IRQ > > parent. > > > > Refer this thread [0] where other SoC vendors have similar issues, > > maybe in future when DTC becomes more clever we can use single SoC > > DTSI for both. > > Not sure, May be the macro suggestion mentioned in that thread will work for us?? > As it is just only the interrupt properties that differ which is > handled in macro. A Generic macro in common dtsi which is > expanded in RISCV or arm64 specific dtsi to get proper one?? I brought it up with the DT people in a separate thread[1]. Please continue the discussion there. Thanks! [1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@xxxxxxxxxxxxxx Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
