Hi Geert,
> > +&msiof0 {
> > + pinctrl-0 = <&msiof0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
>
> I assume you added this becomes Spider has an MSIOF pin header?
Yes, that is one reason. It has it on the extension board. On the CPU
board, MSIOF0 is also connected to the CPLD.
> > +
> > &pfc {
> > pinctrl-0 = <&scif_clk_pins>;
> > pinctrl-names = "default";
> > @@ -116,6 +122,12 @@ mmc_pins: mmc {
> > power-source = <1800>;
> > };
> >
> > + msiof0_pins: msiof0 {
> > + groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd",
> > + "msiof0_txd", "msiof0_ss1", "msiof0_ss2";
>
> MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which
> is used as the power source for various components (but not available
> on the MSIOF0 pin header?), so I'm a but reluctant to add this patch...
Uh, you are right with the voltage selector. I missed that, sorry.
However, it is present on the MSIOF0 connector at pin 1. My suggestion
is to remove SS2 from the PFC node and add a comment describing the
situation?
All the best,
Wolfram
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