Hi Geert, Thank you for the review. On Thu, Aug 18, 2022 at 4:01 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > More info about RZ/Five SoC: > > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -415,11 +415,12 @@ properties: > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > - const: renesas,r9a06g032 > > > > - - description: RZ/G2UL (R9A07G043) > > + - description: RZ/Five and RZ/G2UL (R9A07G043) > > items: > > - enum: > > - renesas,smarc-evk # SMARC EVK > > - enum: > > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > > Should we be consistent, and leave out the "(RISC-V core)" comment, > or add it everywhere? > Rather leave it for now ;) . If Rob agrees on your suggestion on splitting (renesas,{rmobile,rcar-gen[1234],rza,rzg,rzn,...}.yaml that would make it cleaner. > Note that several of the SoCs listed in this file have SuperH or > RealTime ARM cores, so going for the former means a lot of work. > Agreed. Cheers, Prabhakar
