Hi Conor,
On Tue, Jul 26, 2022 at 7:25 PM <Conor.Dooley@xxxxxxxxxxxxx> wrote:
>
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
:)
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
My plan was to get the initial minimal SoC DTSi and then later
gradually add the board DTS, but it looks like I'll have to include it
along with this series.
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
I shall include the Makefile and boards dts in v2
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..6e0b640c6c7f
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
>
> Including arm gic stuff on riscv? That seems a bit odd to me.
>
Ouch this needs to be replaced with irq.h (required for IRQ_TYPE_LEVEL_* flags)
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a07g043";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
>
> Why add the empty value in that case?
>
For ARM64 SoC DTSI we use the above approach so f Iollowed the same,
but you are right this can be dropped.
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + ax45mp: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc: soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scif0: serial@1004b800 {
> > + compatible = "renesas,scif-r9a07g043",
> > + "renesas,scif-r9a07g044";
> > + reg = <0 0x1004b800 0 0x400>;
> > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > + <414 IRQ_TYPE_LEVEL_HIGH>,
> > + <415 IRQ_TYPE_LEVEL_HIGH>,
> > + <413 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eri", "rxi", "txi",
> > + "bri", "dri", "tei";
> > + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > + clock-names = "fck";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > + status = "disabled";
> > + };
> > +
> > + cpg: clock-controller@11010000 {
> > + compatible = "renesas,r9a07g043-cpg";
> > + reg = <0 0x11010000 0 0x10000>;
> > + clocks = <&extal_clk>;
> > + clock-names = "extal";
> > + #clock-cells = <2>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + sysc: system-controller@11020000 {
> > + compatible = "renesas,r9a07g043-sysc";
> > + reg = <0 0x11020000 0 0x10000>;
> > + status = "disabled";
> > + };
> > +
> > + pinctrl: pinctrl@11030000 {
> > + compatible = "renesas,r9a07g043-pinctrl";
> > + reg = <0 0x11030000 0 0x10000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + gpio-ranges = <&pinctrl 0 0 152>;
> > + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_GPIO_RSTN>,
> > + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > + };
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <543>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
>
> Does reg not usually get sorted after compatible?
> For consistency in this file it should at least.
>
Agreed will fix that.
Cheers,
Prabhakar
