This is a follow-up to the series "[PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC"[1]. The change made there is also needed for the already-supported T-HEAD C9xx PLIC. So this binding change is necessary before I can send the Allwinner D1 devicetree. [1]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/T/ Changes in v1: - Use a flag for enabling the changes instead of a variant ID - Use handle_edge_irq instead of handle_fasteoi_ack_irq - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL Samuel Holland (3): dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC irqchip/sifive-plic: Name the chip more generically irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling .../sifive,plic-1.0.0.yaml | 31 ++++++- drivers/irqchip/irq-sifive-plic.c | 91 +++++++++++++++++-- 2 files changed, 108 insertions(+), 14 deletions(-) -- 2.35.1
