Hi All, This patch series adds PLIC support for Renesas RZ/Five SoC. Sending this as an RFC based on the discussion [0]. This patches have been tested with I2C and DMAC interface as these blocks have EDGE interrupts. [0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@xxxxxxxxxx/T/ v1-v2: * Fixed review comments pointed by Marc and Krzysztof. RFC-->v1: * Fixed review comments pointed by Rob and Geert. * Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. RFC: https://lore.kernel.org/linux-renesas-soc/ 20220524172214.5104-2-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/T/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC .../sifive,plic-1.0.0.yaml | 44 ++++++++++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++- 3 files changed, 113 insertions(+), 5 deletions(-) -- 2.25.1
