On 22/06/2022 20:17, Lad Prabhakar wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > amend the RZ/Five CPG clock and reset definitions. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
