Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH] clk: renesas: rzg2l: Fix reset status function
>
> Hi Biju,
>
> On Tue, May 31, 2022 at 9:17 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0
> > means reset signal is not applied (deassert state) and 1 means reset
> > signal is applied (assert state).
> >
> > reset_control_status() expects a positive value if the reset line is
> > asserted. But rzg2l_cpg_status function returns zero for asserted
> > state.
> >
> > This patch fixes the issue by adding double inverted logic, so that
> > reset_control_status returns a positive value if the reset line is
> > asserted.
> >
> > Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L
> > SoC")
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> This bug has been present since v5.14, and went unnoticed so far.
> Is it OK for you to queue this in renesas-clk-for-v5.20, or do you see a
> reason to fast-track this fix to v5.19?
renesas-clk-for-v5.20 should be fine. This issue found while adding reset support
for VSPD. There is 1 user prior to this[1]
[1] https://elixir.bootlin.com/linux/latest/source/drivers/mmc/host/renesas_sdhi_core.c#L576
Cheers,
Biju
