Hi Biju,
On Tue, May 31, 2022 at 9:17 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
> reset signal is not applied (deassert state) and 1 means reset signal
> is applied (assert state).
>
> reset_control_status() expects a positive value if the reset line is
> asserted. But rzg2l_cpg_status function returns zero for asserted
> state.
>
> This patch fixes the issue by adding double inverted logic, so that
> reset_control_status returns a positive value if the reset line is
> asserted.
>
> Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
This bug has been present since v5.14, and went unnoticed so far.
Is it OK for you to queue this in renesas-clk-for-v5.20, or do you see
a reason to fast-track this fix to v5.19?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
