Add POEGG{A,B,C,D} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 28284d537a70..58476519683e 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -360,6 +360,50 @@ gpt7: pwm@10048700 {
status = "disabled";
};
+ poegga: poeg@10048800 {
+ compatible = "renesas,r9a07g044-poeg",
+ "renesas,rzg2l-poeg";
+ reg = <0 0x10048800 0 0x04>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_POEG_A_CLKP>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_POEG_A_RST>;
+ status = "disabled";
+ };
+
+ poeggb: poeg@10048c00 {
+ compatible = "renesas,r9a07g044-poeg",
+ "renesas,rzg2l-poeg";
+ reg = <0 0x10048c00 0 0x04>;
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_POEG_B_CLKP>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_POEG_B_RST>;
+ status = "disabled";
+ };
+
+ poeggc: poeg@10049000 {
+ compatible = "renesas,r9a07g044-poeg",
+ "renesas,rzg2l-poeg";
+ reg = <0 0x10049000 0 0x04>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_POEG_C_CLKP>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_POEG_C_RST>;
+ status = "disabled";
+ };
+
+ poeggd: poeg@10049400 {
+ compatible = "renesas,r9a07g044-poeg",
+ "renesas,rzg2l-poeg";
+ reg = <0 0x10049400 0 0x04>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_POEG_D_RST>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g044-ssi",
"renesas,rz-ssi";
--
2.25.1
