[RFC 7/8] arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier board

[Biju Das <biju.das.jz@xxxxxxxxxxxxxx>]

Enable POEGG{A,B,C,D} on RZ/{G2,V2}L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 8fb68e95f1d7..f1fb9cecc49b 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -42,6 +42,22 @@ wm8978: codec@1a {
 	};
 };
 
+&poegga {
+	status = "okay";
+};
+
+&poeggb {
+	status = "okay";
+};
+
+&poeggc {
+	status = "okay";
+};
+
+&poeggd {
+	status = "okay";
+};
+
 /*
  * To enable SCIF2 (SER0) on PMOD1 (CN7)
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
-- 
2.25.1