Hi Phil, On Tue, May 3, 2022 at 2:02 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote: > Details of the SoC can be found here: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output > > Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> > Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v3: > - Replace CPG_CORE with CPG_MOD > - Add UART pclk > - Add gic clk > - Fix cpg and uart0 register region > - Remove sys as we are currently not using it and binding not accepted Thanks for the update! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi > + timer { > + compatible = "arm,armv8-timer"; > + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>; > + resets = <&cpg R9A09G011_SYC_RST_N>; As per the discussion about [PATCH v3 04/12], these two properties should be dropped. > + }; > +}; The rest LGTM, so Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
