Hi Geert Uytterhoeven,
Thanks for the feedback.
> Subject: Re: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O
> Bus controller node
>
> Hi Biju,
>
> On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > @@ -418,12 +418,20 @@ adc: adc@10059000 {
> > };
> >
> > sbc: spi@10060000 {
> > + compatible = "renesas,r9a07g043-rpc-if",
> > + "renesas,rzg2l-rpc-if";
> > reg = <0 0x10060000 0 0x10000>,
> > <0 0x20000000 0 0x10000000>,
> > <0 0x10070000 0 0x10000>;
> > + reg-names = "regs", "dirmap", "wbuf";
> > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>
> LGTM, but this interrupt is not documented in the RZ/G2UL Hardware User's
> Manual (Rev. 0.51 and 1.00)?
You are correct. As per Table25.1 and Table 8.2, QSPI_INT# is not available on
RZ/G2UL.
Will Fix this in next version. Maybe we need to make interrupt as optional in bindings with driver changes?
Cheers,
Biju
>
> > + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
> > + <&cpg CPG_MOD R9A07G043_SPI_CLK>;
> > + resets = <&cpg R9A07G043_SPI_RST>;
> > + power-domains = <&cpg>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - /* place holder */
> > + status = "disabled";
> > };
> >
> > cpg: clock-controller@11010000 {
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
