Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L
> MIPI DSI TX bindings
>
> Hi Biju,
>
> On Mon, Mar 28, 2022 at 8:49 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,175 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +title: Renesas RZ/G2L MIPI DSI Encoder
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > +
> > +description: |
> > + This binding describes the MIPI DSI encoder embedded in the Renesas
> > + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
> > +with
> > + up to four data lanes.
> > +
> > +allOf:
> > + - $ref: /schemas/display/dsi-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
>
> Do you want to define SoC-specific compatible values, or can the IP
> revision be read from the hardware?
There is no IP revision register for DSI. "rzg2l-mipi-dsi" is generic
Compatible for both RZ/G2L and RZ/V2L.
So I can add SoC compatible for both these SoC's along with generic one.
Regards,
Biju
>
> The rest LGTM (I'm no MIPI-DSI expert), so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
